The present invention relates generally to semiconductor manufacturing and more particularly to a method for forming a contact to a semiconductor region of a semiconductor device.
In one respect, gallium arsenide semiconductor devices are considered advantageous over silicon semiconductor devices because they are capable of operating at higher speeds. This is due to the fact that electrons have a higher mobility in gallium arsenide than in silicon. However, the speed advantage is not necessarily obtainable unless electrical signals can efficiently be transmitted to and from the semiconductor device. One limitation that can impair transmission of the signals is a poor quality semiconductor device ohmic contact. This can be a significant consideration in gallium arsenide semiconductor manufacturing because the integration scheme required to form high quality electrical connections between ohmic contact materials and semiconductor materials, such as gallium arsenide can be more challenging than that of silicon. Therefore, unless high quality electrical connections can reliably be made, the speed advantages of gallium arsenide over silicon may not necessarily be achieved.
Shown in FIG. 1 is a cross section illustrating of a portion of a gallium arsenide metal semiconductor field effect transistor (MESFET) that includes undoped gallium arsenide semiconductor layers 16 and 20 and aluminum arsenide etch stop layers 18 and 22. Overlying the etch stop layer 22 on either side of the gate electrode 28 are n+ doped gallium arsenide capping layers 24 and overlying the capping layer 24 are metal ohmic contacts 26 (Note that portions of the semiconductor substrate 10 that include the channel region beneath the semiconductor layer 16 have been omitted for simplicity of illustration).
As stated previously, one potentially limiting aspect regarding the speed of a gallium arsenide semiconductor device is the quality of the electrical contact between the ohmic contact 26 and the semiconductor material of capping layer 24 (metal-semiconductor interface). Ideally the contact resistance (Rc) between the ohmic contact 26 and the capping layer 24 is as low as possible. Parameters that can influence contact resistance include the capping layer""s sheet resistance (xcfx81s), its thickness 32, and the transfer length (Lt) 30 of the contact. The transfer length, as understood by one of ordinary skill, is the length over which the voltage across the metal-semiconductor interface is has dropped to 1/e of its peak value at the edge of the contact. The transfer length is thus considered to be the effective electrical length of the ohmic contact and the measurement corresponds to the ohmic contact""s ability to pass current through the metal-semiconductor interface. The transfer length is a function of the specific contact resistance xcfx81c and sheet resistance of the capping layer xcfx81s. Accordingly, with knowledge of the contact technology, i.e. the specific contact resistance xcfx81c and the sheet resistance of the capping layer xcfx81s, the transfer length Lt can be determined by the equation: Lt=[xcfx81c/xcfx81s]xc2xd. However, this relationship is not necessarily valid if the sheet resistance of the capping layer beneath the contact is not equal to the sheet resistance of the capping layer at its full thickness 32. This can be problematic because in reality the sheet resistance of the capping layer underneath the contact is higher that the full thickness capping layer because the ohmic contact encroaches some depth into the capping layer during contact formation. The encroachment correspondingly results in a thinning of the capping layer in these regions.
Shown in FIG. 2 is an illustration of an ohmic contact 27 encroaching (penetrating) into a capping layer 25. Initially after depositing the metal used to form the ohmic contact, the metal lies on the uppermost surface of the capping layer 25 (similar to the ohmic contact 26 and capping layer 24 shown in FIG. 1) such that the bottom surface of the metal is coplanar with the top surface of the capping layer. Then, the substrate is annealed for a predetermined period of time. The annealing process results in encroachment of the ohmic contact 27 into the capping layer 25 to a depth 35. The encroachment reduces the thickness 33 of the capping layer 25 in regions beneath the ohmic contact 27 and effectively increases its sheet resistance. This has the effective of reducing the ohmic contact transfer length (as compared to the transfer length 30 shown in FIG. 1) to produce a reduced effective transfer length 31. The reduction in transfer length correspondingly results in increased contact resistance of the ohmic contact 27, which potentially results in a slower semiconductor device.
One proposed solution to the contact encroachment problem includes increasing the overall of capping layer thickness; thereby making the conductivity change caused by the encroachment small relative to the conductivity of the overall capping layer. To accomplish this, the capping layer 25 should be made significantly thicker than the encroachment depth. Thus, given an encroachment depth of approximately 600 to 700 angstroms and a requirement that the capping layer thickness be approximately 10 times thicker than the encroachment depth, the capping layer should have a thickness of approximately 0.6 to 0.7 microns. Unfortunately at this thickness such an approach is unattractive due to the additional processing costs, the impact to cycle time and subsequent processing integration concerns, such as etching the increased capping layer thickness. Accordingly, alternative solutions for the encroaching problem are desirable.